Texas Instruments TSW14J59EVM Evaluation Module (EVM)
Texas Instruments TSW14J59EVM Evaluation Module (EVM) is a next-generation pattern generator and data capture card used to evaluate performances of the current TI JESD204C_B device family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a JESD204C_B interface when using a high-quality, low-jitter clock and a high-quality input frequency, the TSW14J59 can be used to demonstrate data sheet performance specifications. Using the Texas Instruments JESD201C IP core, the TSW14J59EVM can be dynamically configurable to support lane speeds from 1Gbps to 32Gbps, from 1 to 16 lanes. Together with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), the TSW14J59EVM is a complete system that captures and evaluates data samples from the ADC evaluation module, generates and sends desired test patterns to DAC evaluation modules, and performs both tasks at the same time with AFE evaluation modules (transceiver mode).Features
- Backward-compatible with JESD204B (Subclasses: 0, 1, 2)
- Support for deterministic latency
- Serial lanes speed up to 32Gbps
- 16 routed transceiver channels
- 24Gb DDR4 SDRAM (split into two banks of 3 independent 256 × 16, 4Gb SDRAMs)
- Quarter-rate DDR4 controllers supporting up to 1200MHz operation
- 1.536G of 16-bit samples of on-board memory
- Supports 1.8V CMOS IO standard for spare FMC+ signals
- General purpose 200MHz oscillator
- On-board Cypress USB FX3 USB 3.0 device for parallel interface to the FPGA and general purpose I/O interface to on-board functions and FMC+
- On-board Digilent JTAG SMT2 programmer for FPGA JTAG interface for downloading firmware
- Reference clocking for transceivers available through FMC+ port or SMAs
- Supported by TI HSDC PRO software
- FPGA firmware developed with Xilinx Vivado development tool
- TI JESD RX IP core with support for
- USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
- ILA configuration data is accessible through USB and JTAG
- Lane alignment and character replacement enabled or disabled through USB and JTAG
- TI JESD TX IP core with support for
- USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
- ILA configuration data is accessible through USB and JTAG
- Dynamically reconfigurable Transceiver data rate.
- Serial lane operating range from 1 to 32Gbps
- TI JESD RX IP core with support for
Block Diagram
Publicado: 2024-04-08
| Actualizado: 2024-04-16
