AD9546BCPZ

Name: Analog Devices Inc. AD9546BCPZ
Brand: Analog Devices
SKU: 584-AD9546BCPZ
Price: 49573 CLP
Availability: InStock

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Mouser #:

584-AD9546BCPZ

Mfr. #:

AD9546BCPZ

Mfr.:

Analog Devices

Description:

Clock Synthesizer / Jitter Cleaner Dual DPLL Digitized Clock Synchronizer

Datasheet:

AD9546BCPZ Datasheet

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Analog Devices Inc.
Product Category:	Clock Synthesizer / Jitter Cleaner
RoHS:
Number of Outputs:	10 Output
Max Output Freq:	500 MHz
Output Level:	CML, HCSL, LVDS
Input Level:	Differential, Single-Ended
Package / Case:	LFCSP-48
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	1.89 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Packaging:	Tray
Brand:	Analog Devices
Development Kit:	AD9546/PCBZ
Moisture Sensitive:	Yes
Operating Supply Current:	325 mA
Pd - Power Dissipation:	760 mW
Product:	Clock Synchronizers
Product Type:	Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity:	260
Subcategory:	Clock & Timer ICs
Type:	DPLL Digitized

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Datasheet

AD9546BCPZ Datasheet

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Compliance Codes

CNHTS:: 8542399000
CAHTS:: 8542390000
USHTS:: 8542390090
MXHTS:: 8542399999
ECCN:: EAR99

Origin Classifications

Country of Origin:: Korea, Republic of
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

AD9546 Dual DPLL Digitized Clock Synchronizer

Analog Devices Inc. AD9546 Dual DPLL Digitized Clock Synchronizer combines digitized clocking technology that efficiently transports and distributes clock signals in systems. Digitized clocking on the AD9546 allows the design of flexible and scalable clock transport systems with well-controlled phase (time) alignment. The AD9546 is ideal for the design of network equipment that must meet the synchronization requirements for IEEE^® 1588™ boundary clocks per ITU-T G.8273.2 Class D. Additionally, digitized clocking is also relevant in applications requiring the accurate transport of frequency and phase to multiple usage endpoints, such as, distributing synchronized system reference (SYSREF) clocks to an array of ADC channels.