DDR2 SDRAM
ISSI DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ISSI DDR2 SDRAM has on-die termination (ODT) and programmable burst lengths of 4 or 8. The on-chip DLL aligns DQ and DQs transitions with CK transitions.
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